bare-metal-bringup
Use when bringing up bare-metal or kernel code on a new architecture, SoC, or board (RISC-V, ARM, x86, ESP32) and it won't boot,…
Use when building or debugging a compiler backend, codegen, or assembler and you need to prove the generated machine code is correct by executing it on a real CPU or a fast emulator, not just inspecting the output
Claude Code
$ npx -y skills add lilithsemi/claude-for-hardware --skill codegen-validation --agent claude-code
Codex
$ npx skills add lilithsemi/claude-for-hardware --skill codegen-validation -a codex -y
Cursor
$ npx skills add lilithsemi/claude-for-hardware --skill codegen-validation -a cursor -y
Gemini CLI
$ npx skills add lilithsemi/claude-for-hardware --skill codegen-validation -a gemini-cli -y
GitHub Copilot
$ npx skills add lilithsemi/claude-for-hardware --skill codegen-validation -a github-copilot -y
OpenCode
$ npx skills add lilithsemi/claude-for-hardware --skill codegen-validation -a opencode -y
Windsurf
$ npx skills add lilithsemi/claude-for-hardware --skill codegen-validation -a windsurf -y
name: codegen-validation description: Use when building or debugging a compiler backend, codegen, or assembler and you need to prove the generated machine code is correct by executing it on a real CPU or a fast emulator, not just inspecting the output
A codegen backend is correct when the code it emits computes the right answer on a real machine. Reading the assembly proves nothing; a plausible-looking instruction sequence with a wrong ABI detail or a clobbered callee-saved register passes every eyeball review and fails on hardware.
**Core principle:** Execution-validate. Compile a known program, run the output on a real CPU or a fast emulator, and assert the observed result. If you didn't run it, you don't know it works.
known program (expected result known) -> codegen -> machine code -> run on real CPU / fast emulator -> assert observed result == expected
Execution validation reliably catches the codegen bugs that look fine on paper:
These are exactly the bugs that turn into silicon respins or weeks of "intermittent" debugging if they escape. A handful of executed tests finds them in seconds.
Order tests so each new one depends only on capabilities already validated:
1. Return a constant (codegen + run harness works at all). 2. Arithmetic on arguments (ABI in, result out). 3. Stack frame (alloca, alignment, prologue/epilogue). 4. Calls (the full ABI, callee-saved save/restore, return address). 5. Control flow (branches, loops, phi/select). 6. Spilling (more live values than registers).
When a higher test fails and the lower ones pass, the bug is in the new capability. That ordering is the debugger.
| Smell | Do instead | |-------|------------| | "The disassembly looks correct" | Execute it and assert the result | | Test asserts "no crash" | Assert the actual computed value | | Slow full-system sim per test | Fast target emulator, run every build | | One big program as the only test | Capability-ordered tests, smallest first | | Skipping ABI/spill tests | Those are exactly where the bugs hide |
Claude Code skills for hardware design, validation, and bring-up. A plugin of focused skills that teach Claude how to do real hardware work: designing reusable HDL, integrating an SoC, bringing up FPGAs and bare-metal targets, building firmware boot chains,
Use when bringing up bare-metal or kernel code on a new architecture, SoC, or board (RISC-V, ARM, x86, ESP32) and it won't boot,…
Use when verifying a hardware DUT (a CPU core, FPGA, or netlist) against a golden reference model, building coverage-guided…
Use when building or debugging a firmware and boot chain (RISC-V SBI, UEFI, ACPI, a bootloader handoff like Limine to an OS) or…
Use when loading a bitstream onto a physical FPGA and driving or observing it over JTAG or GPIO, especially bit-banged JTAG from…
Use when synthesizing RTL to an FPGA with yosys/nextpnr (ECP5/Lattice and similar), fighting area or routing congestion,…
Use when writing, refactoring, or deciding how to test an HDL module, component, or IP block (ROHD, Chisel, SpinalHDL, Verilog,…
You MUST use this before any creative work - creating features, building components, adding functionality, modifying behavior, or…
Ask which skill or flow fits your situation. A router over the skills in this repo.