Claude Code skills for hardware work: designing HDL, integrating SoCs, bringing up FPGAs and bare-metal boards, building firmware boot chains, and verifying hardware and compiler output against reference models.
@midstallUse when bringing up bare-metal or kernel code on a new architecture, SoC, or board (RISC-V, ARM, x86, ESP32) and it won't boot,…
@midstallUse when building or debugging a compiler backend, codegen, or assembler and you need to prove the generated machine code is…
@midstallUse when verifying a hardware DUT (a CPU core, FPGA, or netlist) against a golden reference model, building coverage-guided…
@midstallUse when building or debugging a firmware and boot chain (RISC-V SBI, UEFI, ACPI, a bootloader handoff like Limine to an OS) or…
@midstallUse when loading a bitstream onto a physical FPGA and driving or observing it over JTAG or GPIO, especially bit-banged JTAG from…
@midstallUse when synthesizing RTL to an FPGA with yosys/nextpnr (ECP5/Lattice and similar), fighting area or routing congestion,…
@midstallUse when writing, refactoring, or deciding how to test an HDL module, component, or IP block (ROHD, Chisel, SpinalHDL, Verilog,…
@midstallUse when packaging EDA or hardware toolchains in Nix (Yosys, OpenROAD, simulators, vendor tools) and hitting…
@midstallUse when implementing a hardware block, protocol, peripheral, or ISA feature in ROHD and you should ground it in the…
@midstallUse when building or testing RTL in ROHD (Dart), rohd_bridge, or rohd_hcl and hitting hierarchy-violation errors, "Bad state: No…
@midstallUse when optimizing RTL microarchitecture for area or clock frequency (Fmax), a design is too big to fit or too slow to meet…
@midstallUse when writing hardware, firmware, verification, or tooling code that will reach real silicon, and you face a tradeoff between…
@midstallUse this agent when bare-metal code, firmware, or an FPGA design will not come up on real hardware: it boots but hangs, faults…
@midstallUse this agent to review HDL/RTL changes (ROHD, Chisel, SpinalHDL, Verilog, VHDL) before merge or tapeout. It reviews a diff or a…
@midstallUse this agent before a tapeout or MPW shuttle submission to run the precheck gate and decide whether the design is genuinely…
@midstallDrive the measure-don't-guess FPGA fit and timing loop on a design
@midstallDrive the hardware bring-up checkpoint ladder when something won't come up
@midstallRun the tapeout precheck gate on a design before submission
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