/spice

name: spice
description: >-
  Run automatic SPICE simulations on subcircuits detected from KiCad schematic
  analysis — validates filter frequencies, divider ratios, opamp gains, LC
  resonance, and crystal load capacitance. Supports ngspice, LTspice, and Xyce
  (auto-detected). Generates testbenches, runs batch mode, produces structured
  pass/warn/fail report. Use when the user asks to simulate, verify, or
  validate any analog subcircuit — RC filters, LC filters, voltage dividers,
  opamp circuits, crystal oscillators. Also for "simulate my circuit", "run
  spice", "verify with simulation", "check my filter cutoff", "does this
  divider give the right voltage", "what's the bandwidth of this opamp stage".
  Consider suggesting simulation during design reviews when the schematic
  analyzer reports simulatable subcircuits and a SPICE simulator is available.

SPICE Simulation Skill

Automatically generates and runs SPICE testbenches for circuit subcircuits detected by the `kicad` skill's schematic analyzer. Supports ngspice, LTspice, and Xyce (auto-detected). Validates calculated values (filter frequencies, divider ratios, opamp gains) against actual simulation results and produces a structured report.

This skill inverts the typical simulation workflow: instead of requiring users to create simulation sources and configure analysis (which ~2.5% of KiCad users do), it generates targeted testbenches automatically from the analyzer's subcircuit detections.

Related Skills

| Skill | Purpose | |-------|---------| | `kicad` | Schematic/PCB analysis — produces the analyzer JSON this skill consumes | | `digikey` | Parametric specs for behavioral models, datasheet downloads | | `mouser` | Parametric specs (secondary source), datasheet downloads | | `lcsc` | Parametric specs (no auth needed), datasheet downloads | | `element14` | Parametric specs (international), datasheet downloads | | `emc` | EMC pre-compliance — uses this skill's simulator infrastructure for SPICE-enhanced PDN impedance and EMI filter analysis |

**Handoff guidance:** The `kicad` skill's `analyze_schematic.py` produces the analysis JSON with subcircuit detections in the flat `findings[]` array (filtered by `detector` field). This skill reads that JSON, generates SPICE testbenches for simulatable subcircuits, runs the detected simulator (ngspice/LTspice/Xyce), and produces a structured verification report. Always run the schematic analyzer first. During a design review, run simulation after the analyzer and before writing the final report — simulation results should appear as a verification section in the report. The `emc` skill reuses this skill's simulator backend for SPICE-enhanced PDN impedance and EMI filter insertion loss checks — when ngspice is available, the EMC skill's `--spice-enhanced` flag activates these checks automatically.

Requirements

• **A SPICE simulator** — one of the following (auto-detected, first available wins):
• **ngspice** — `sudo apt install ngspice` (Linux) / `brew install ngspice` (macOS) / ngspice.sourceforge.io (Windows). Most common choice.
• **LTspice** — free from analog.com/ltspice. Popular on Windows, works via wine on Linux.
• **Xyce** — from xyce.sandia.gov. Parallel SPICE for large circuits.
• Override with `--simulator ngspice|ltspice|xyce` or `SPICE_SIMULATOR` env var.
• **Python 3.10+** — stdlib only, no pip dependencies
• **Schematic analyzer JSON** — from `analyze_schematic.py --output`

If no simulator is installed, skip simulation gracefully and note it in the report. Do not treat a missing simulator as an error — it's an optional enhancement.

Workflow

Step 1: Run the schematic analyzer

python3 <kicad-skill-path>/scripts/analyze_schematic.py design.kicad_sch --analysis-dir analysis/

Step 2: Run SPICE simulations

Pass `--analysis-dir analysis/` — the script auto-resolves `schematic.json` from the manifest's current run, writes `spice.json` into the same run folder, and parks intermediate `.cir` / `.raw` files at `<run>/spice_work/` by default.

# Recommended: auto-resolve schematic + write spice.json into the current run
python3 <skill-path>/scripts/simulate_subcircuits.py --analysis-dir analysis/

# Explicit form — positional or --schematic path
python3 <skill-path>/scripts/simulate_subcircuits.py analysis.json --output sim_report.json

# Simulate specific types only
python3 <skill-path>/scripts/simulate_subcircuits.py --analysis-dir analysis/ --types rc_filters,voltage_dividers

# Keep simulation files for debugging (default: <run>/spice_work/ when --analysis-dir is set, else a temp dir)
python3 <skill-path>/scripts/simulate_subcircuits.py --analysis-dir analysis/ --workdir ./spice_runs

# Increase timeout for complex circuits (default: 5s per subcircuit)
python3 <skill-path>/scripts/simulate_subcircuits.py --analysis-dir analysis/ --timeout 10

# Omit file paths from output (cleaner for reports)
python3 <skill-path>/scripts/simulate_subcircuits.py --analysis-dir analysis/ --compact

Step 2b (optional): PCB parasitic-aware simulation

When both schematic and PCB exist, run parasitic-annotated simulation for more accurate results on analog circuits:

# Analyze PCB with full trace segment detail
python3 <kicad-skill-path>/scripts/analyze_pcb.py design.kicad_pcb --full --output pcb.json

# Extract parasitic R/L/C from PCB geometry
python3 <skill-path>/scripts/extract_parasitics.py pcb.json --output parasitics.json

# Run simulation with PCB parasitics injected into testbenches
python3 <skill-path>/scripts/simulate_subcircuits.py analysis.json --parasitics parasitics.json --output sim_report.json

With `--parasitics`, testbenches include trace resistance and via inductance between components. The report shows the parasitic impact — e.g., "48mΩ trace resistance shifts RC filter fc down 0.3%."

**When to use parasitic simulation:** Consider it when the design has high-impedance feedback networks (>100kΩ),