bom
BOM (Bill of Materials) management for electronics projects — the workflow skill that coordinates DigiKey, Mouser, LCSC,…
EMC pre-compliance risk analysis for KiCad PCB designs — 18 check categories, 44 rule IDs covering ground planes, decoupling, I/O filtering, switching harmonics, clock routing, differential pair skew, board edge radiation, PDN impedance, return paths, crosstalk, ESD protection,
Claude Code
$ npx -y skills add aklofas/kicad-happy --skill emc --agent claude-code
Codex
$ npx skills add aklofas/kicad-happy --skill emc -a codex -y
Cursor
$ npx skills add aklofas/kicad-happy --skill emc -a cursor -y
Gemini CLI
$ npx skills add aklofas/kicad-happy --skill emc -a gemini-cli -y
GitHub Copilot
$ npx skills add aklofas/kicad-happy --skill emc -a github-copilot -y
OpenCode
$ npx skills add aklofas/kicad-happy --skill emc -a opencode -y
Windsurf
$ npx skills add aklofas/kicad-happy --skill emc -a windsurf -y
name: emc description: >- EMC pre-compliance risk analysis for KiCad PCB designs — 18 check categories, 44 rule IDs covering ground planes, decoupling, I/O filtering, switching harmonics, clock routing, differential pair skew, board edge radiation, PDN impedance, return paths, crosstalk, ESD protection, shielding, and magnetic leakage from switching inductors. Produces severity-ranked risk report with pre-compliance test plan. Supports FCC Part 15, CISPR 32, CISPR 25 (automotive), MIL-STD-461G. SPICE-enhanced when available. Use when the user asks about EMC, EMI, radiated/conducted emissions, FCC compliance, CE marking, CISPR, ground plane issues, decoupling strategy, clock routing EMC, switching noise, differential pair skew, or whether their board will pass EMC testing. Also for "will this pass FCC?", "check my EMC", "is my ground plane okay?", "check my decoupling", or "generate an EMC test plan".
Automated EMC risk analysis for KiCad PCB designs. Identifies the most common causes of EMC test failures using geometric rule checks, analytical emission formulas, and optional SPICE simulation.
**This is a risk analyzer, not a compliance predictor.** It catches ~70% of common EMC design mistakes before fabrication. It cannot guarantee FCC/CISPR compliance — only a calibrated measurement in an accredited lab can do that. But it can reduce the first-spin failure rate from ~50% toward ~20-30%, potentially saving $5K-$50K per avoided board respin.
| Skill | Purpose | |-------|---------| | `kicad` | Schematic/PCB analysis — produces the analyzer JSON this skill consumes | | `kicad` (thermal) | Thermal hotspot analysis — MLCC derating and ferrite/inductor overheating findings can amplify EMC decoupling and filter issues (an over-stressed MLCC degrades; a hot ferrite drifts impedance). Worth cross-checking when EMC flags DC-001/DC-002 or EF-001/EF-002. | | `spice` | SPICE simulation — provides simulator backend for SPICE-enhanced PDN/filter checks |
**Handoff guidance:** Run the `kicad` skill's `analyze_schematic.py` and `analyze_pcb.py --schematic` first — this skill consumes their JSON output. Use `--full` on the PCB analyzer for best results (enables per-track coordinates for ground plane crossing, edge proximity, and return path checks). During a design review, run EMC analysis after the schematic/PCB analyzers, SPICE simulation, and thermal analysis, then incorporate EMC findings into the report.
python3 <kicad-skill-path>/scripts/analyze_schematic.py design.kicad_sch --analysis-dir analysis/ python3 <kicad-skill-path>/scripts/analyze_pcb.py design.kicad_pcb --full --schematic analysis/<run_id>/schematic.json --analysis-dir analysis/
Pass `--analysis-dir analysis/` — the script auto-resolves `schematic.json` and `pcb.json` from the manifest's current run, and writes `emc.json` into the same folder so the manifest tracks it.
# Recommended: auto-resolve inputs from the current run
python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/
# Equivalent — explicit paths still accepted (and required if you want to
# point at a non-current run or override one input)
python3 <skill-path>/scripts/analyze_emc.py \
--schematic analysis/<run_id>/schematic.json \
--pcb analysis/<run_id>/pcb.json \
--analysis-dir analysis/
# One-off JSON (bypasses the cache)
python3 <skill-path>/scripts/analyze_emc.py --schematic schematic.json --pcb pcb.json --output emc.json
# SPICE-enhanced (improved PDN and filter accuracy)
python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --spice-enhanced
# Select target standard
python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --standard cispr-class-b
# Select target market (sets all applicable standards)
python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --market eu
# Filter by severity (high = error findings only)
python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --severity high
# Human-readable text output
python3 <skill-path>/scripts/analyze_emc.py --analysis-dir analysis/ --textFor spectral lines that are already expressed as RMS dBµV, dBµV/m, or dBµA, use the standalone screen. Levels must be RMS: subtract 3.01 dB from peak-amplitude spectra first. This skill's `harmonic_spectrum()` gives switch-node source amplitudes, not emission levels, so it is not a valid input without a coupling/path model.
**Limit values must come from the user.** Build a limit profile only from limit values the user provides, together with their source (for example a standard's edition and table or clause, where applicable), and record that source in `source.citation`. Never write limit tables from memory or fill in missing bands, detectors, or units; if the user has not supplied limits, ask for them instead of running the screen.
python3 <skill-path>/scripts/analyze_harmonic_limits.py \ --spectrum harmonic-lines.json \ --limits limit-profile.json \ --limit-column peak \ --output harmonic-limit-screen.json
This command is separate from `analyze_emc.py`. It does not calculate a spectrum, add an EMC finding, change the risk score, write `emc.json`, or determine compliance. See [Harmonic-Limit Screening](references/harmonic-limit-screen.md) for the input schemas and interpretation boundary.
AI-powered design review for KiCad. Analyzes schematics, PCB layouts, and Gerbers. Catches real bugs before you order boards.
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