gateflow-plugin

GateFlow Plugin for Claude Code

AI-powered hardware development platform — design, verify, synthesize, and deploy working RTL with natural language. Supports SystemVerilog, Verilog, and VHDL across the full open-source FPGA toolchain.

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Loving hardware doesn't have to be gatekept.

GateFlow brings professional hardware development tooling to Claude Code. Describe what you want to build — including your target board — and get lint-checked, simulated, formally verified, synthesis-ready code with correct pin assignments.

Whether you're writing your first always_ff, formally proving your FIFO never overflows, or synthesizing an SPI controller for your Arty A7, the tools should help you, not fight you.

We can't wait to see what you create. ❤️

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• Quick Start — Install in one command
• Usage — Natural language, skills, and commands
• Features — What makes GateFlow different
• Components — All skills, agents, and commands
• Individual Downloads — Grab single components
• Cross-Tool Compatibility — Use with Codex, Cursor, Copilot, Cline, Windsurf
• Configuration — Project-specific settings
• Project Structure — Repo layout
• Troubleshooting — Common issues
• Updates — Changelog
• Releases — Detailed release notes
• Contributing | License | Links

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Quick Start

Install

# Option 1: Marketplace (recommended)
claude plugin marketplace add codejunkie99/Gateflow-Plugin
claude plugin install gateflow

# Option 2: Clone and run
git clone https://github.com/codejunkie99/Gateflow-Plugin.git
claude --plugin-dir ./Gateflow-Plugin/plugins/gateflow

# Option 3: Persistent (add to ~/.claude/settings.json)
git clone https://github.com/codejunkie99/Gateflow-Plugin.git ~/.claude-plugins/gateflow-marketplace

For Option 3, add to ~/.claude/settings.json or .claude/settings.json:

{
  "plugins": [
    "~/.claude-plugins/gateflow-marketplace/plugins/gateflow"
  ]
}

Prerequisites

Tool	Required	macOS	Linux
Claude Code	Yes	See website	See website
Verilator	Recommended	brew install verilator	sudo apt install verilator
Verible	Optional	brew tap chipsalliance/verible && brew install verible	See releases
Yosys	For synthesis	brew install yosys	sudo apt install yosys
SymbiYosys	For formal	pip install symbiyosys	pip install symbiyosys
GHDL	For VHDL	brew install ghdl	sudo apt install ghdl
nextpnr	For P&R	brew install nextpnr	See GitHub
openFPGALoader	For flash	brew install openfpgaloader	See GitHub

Verify & Update

# Verify installation
/gf-doctor

# Update (marketplace)
# /plugin → Marketplaces → gateflow → Update → restart Claude Code

# Update (local)
# git pull in your plugin folder, then restart Claude Code

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Usage

Just Ask

GateFlow understands context. Describe what you need in plain English:

"Create a FIFO and test it"
 → Generates FIFO, creates testbench, runs simulation, fixes issues, delivers working code

"Formally verify that the FIFO never overflows"
 → Generates SVA properties, configures SymbiYosys, runs proof, reports results

"Synthesize my design for the iCEBreaker board"
 → Runs Yosys synthesis, reports LUT/FF/BRAM usage, generates constraint file

"Add an SPI controller to my project"
 → Installs verified SPI master IP block with testbench and formal proofs

"What pins does the Arty A7 PMOD JA have?"
 → Looks up curated board database, shows pin assignments with I/O standards

"Why is my output X?"
 → Analyzes code, traces signal path, identifies root cause

"Plan a DMA controller"
 → Creates detailed design plan with block diagrams, FSMs, interfaces, verification strategy

Skills (Auto-Activating)

Skills activate automatically based on context:

Skill	Trigger	What It Does
/gf	Any SV task	Main orchestrator — plan-first, parallel build, verify until working
/gf-plan	"plan", "design", "architect"	RTL implementation plans with ASCII diagrams
/gf-build	"build", "multi-component", "SoC"	Parallel component build orchestration
/gf-formal	"formally verify", "prove", "check property"	Formal verification from natural language via SymbiYosys
/gf-synth	"synthesize", "area estimate", "resource usage"	Yosys synthesis with LUT/FF/BRAM/DSP reports
/gf-architect	"map codebase", "analyze project"	Codebase map with hierarchy, FSMs, clocks, CDC
/gf-viz	"visualize", "show hierarchy"	Terminal ASCII visualization of RTL architecture
/gf-learn	"teach me", "exercise", "practice"	Learning mode with exercises and feedback

Commands

Command	What It Does
/gf-lint	Run Verilator lint with structured output
/gf-fix	Auto-fix lint errors
/gf-sim	Compile and run simulation
/gf-formal	Run SymbiYosys formal verification
/gf-gen	Generate module/testbench scaffolds
/gf-ip	Manage verified IP block library (add/list/info)
/gf-boards	List supported FPGA boards and query pinouts
/gf-demo	One-command zero-config showcase project
/gf-scan	Index project files
/gf-map	Map codebase architecture
/gf-doctor	Check environment and dependencies
/gf-tui	Open the local GateFlow terminal console
/gf-release	Validate plugin release readiness

Local CLI

GateFlow also ships with a command-first local CLI for plugin maintenance and agent creation:

python3 tools/gateflow_cli.py status
python3 tools/gateflow_cli.py agents list
python3 tools/gateflow_cli.py agents create "CDC Reviewer" \
  --role "clock-domain crossing reviewer" \
  --description "Reviews synchronizers and CDC constraints"
python3 tools/gateflow_cli.py shell
python3 tools/gateflow_cli.py tui

Inside the TUI, press a to create a new agent without leaving the dashboard.

Example Session

$ claude --plugin-dir ./Gateflow-Plugin/plugins/gateflow

You: Create a parameterized counter with enable and test it

Claude: Creating counter module...
✓ Created counter.sv

Running lint check...
✓ Lint clean

Creating testbench...
✓ Created tb_counter.sv

Running simulation...
✓ All tests pass (12 checks)

Done! Created:
- rtl/counter.sv (8-bit parameterized counter with enable)
- tb/tb_counter.sv (Self-checking testbench)

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Features

Working Code, Not Just Generated Code

The /gf orchestrator doesn't stop at generation — it verifies:

Create → Lint → Fix → Test → Fix → Formally Verify → Synthesize → Deliver

Formal Verification from Natural Language

Tell GateFlow what to prove in plain English:

"Formally verify that the FIFO never overflows and the pointers are always consistent"
 → Generates SVA assert property statements
 → Configures SymbiYosys (.sby file)
 → Runs bounded model checking
 → Reports proof results or explains counterexamples in English

Yosys Synthesis with Resource Reports

"Synthesize my design for the iCEBreaker"
 → Checks for unsupported SV constructs (warns before failing)
 → Runs Yosys synthesis targeting iCE40
 → Reports: LUTs: 142, FFs: 87, BRAM: 1, DSP: 0

Drop-In IP Library

8 verified, formally proven IP blocks ready to use:

/gf-ip add fifo_sync    → Installs FIFO with RTL + testbench + formal proofs
/gf-ip add uart          → UART TX+RX with configurable baud rate
/gf-ip add axi4lite_slave → AXI4-Lite register interface

Every block is lint-clean, simulation-tested, and formally verified.

Board-Aware Development

GateFlow knows your FPGA board's pinout:

/gf-boards arty-a7-35t pmod-ja  → Shows exact pin assignments

Curated constraint files (.xdc, .pcf, .cst) for popular boards included.

Hardware Design Planning

/gf-plan creates professional design documents:

• Block diagrams (ASCII and Mermaid)
• Module hierarchy and interface specs
• FSM state diagrams
• Clock domain analysis
• Verification strategy and implementation phases

Codebase Intelligence

/gf-architect maps your entire project:

• Module hierarchy and dependencies
• Signal flow analysis and FSM extraction
• Clock domain crossing detection
• Package and type definitions

Comprehensive Coverage

• Memory: FIFOs, dual-port RAM, register files
• Error handling: ECC, watchdogs, TMR
• DFT: Scan chains, JTAG, BIST
• Timing: Retiming, pipelining, SDC
• Verification: SVA, coverage, formal

Smart Hooks

GateFlow watches your workflow and helps proactively:

• After SV edits — reminds you to lint
• Before destructive commands — warns if you're about to delete SV files
• On session end — checks if you forgot to lint or simulate modified files
• Progressive tips — surfaces slash commands you haven't used yet

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Components

Skills (27)

Skill	Description	Source
gf	Main orchestrator — plan, build, verify until working	SKILL.md
gf-plan	RTL implementation planning with diagrams	SKILL.md
gf-build	Parallel component build orchestration	SKILL.md
gf-formal	Formal verification from natural language (SymbiYosys)	SKILL.md
gf-synth	Yosys synthesis with area/timing reports	SKILL.md
gf-ip	IP block library — verified drop-in components	SKILL.md
gf-architect	Codebase map with hierarchy, FSMs, clocks, CDC	SKILL.md
gf-lint	Structured Verilator lint checking	SKILL.md
gf-sim	Simulation with auto DUT/TB detection	SKILL.md
gf-viz	Terminal visualization of RTL architecture	SKILL.md
gf-learn	Learning mode — exercises, reviews, hints	SKILL.md
gf-errors	3-layer error translation for hardware tools	SKILL.md
gf-project	Project context (.gateflow/project.yaml) management	SKILL.md
gf-router	Intent classification and routing	SKILL.md