# verilog-generator

Helps create, review, annotate, repair, refactor, and validate readable synthesizable Verilog RTL for FPGA design, including analysis of existing code.

- Tier: Indexed (plain plugin)
- Category: Code Generation
- Page: https://www.flowy.sh/listings/eriemon-verilog-generator
- Source: https://github.com/Eriemon/verilog-generator
- Price: free and open source

## Summary
Install it with the command on its page. It includes verilog-generator. Its skills do not fire on their own yet. Free and open source.

## Install (Claude Code)
```
npx -y skills add Eriemon/verilog-generator --agent claude-code
```

## Skills
- verilog-generator

## FAQ

### What is verilog-generator?
Helps create, review, annotate, repair, refactor, and validate readable synthesizable Verilog RTL for FPGA design, including analysis of existing code.

### How do I install verilog-generator?
Run these in Claude Code: npx -y skills add Eriemon/verilog-generator --agent claude-code. Then prompt normally.

### Does verilog-generator auto-invoke its skills?
Not yet. It is indexed on Flowy as a plain plugin.

### Is verilog-generator free?
Yes. Flowy is free and open source, with nothing gated. You can read every skill in full before you install.